In computer systems, logic chips and modules (modules may be thermal conduction modules (TCMs) or normal cards) are connected together through wires that rum through a board. In many cases the number of conductors which connect these chips through the module or module to the board are a limiting factor in the design of the computer system. This application presents a method for reducing the number of these connections by approximately half with minimal impact on the design of the system. The method involves sending two signals on each wire connection in a time multiplexed fashion. Previous schemes have been proposed using this technique but have required double frequency clocking schemes or registers, which are very difficult to implement. The system being disclosed herein only requires a skewed clock rather than double-frequency clocks to registers. U.S. Pat. No. 4,926,432 of Zukowski entitled "Time-Division-Multiplexed Data Transmission System" illustrates a time-division-multiplex data transmission system that employs a skewing network to selectively skew each of a plurality of input signals by successively increasing integral multiples of the average period of the multiplex output signal. The skewed signals are merged in a combinatorial merging network having substantially identical delay times and data path to provide a multiplexed signal. In an embodiment shown, the invention provides a time-division-multiplexer in which the incoming signals are precoded prior to being skewed by a skewing network, so that the form of the multiplex output signal is a conventional sequentially interleaved input signal as provided by the prior art multiplexers, and the merging network is a binary tree EXCLUSIVE OR (XOR) gate array. Another multiplexing circuitry is shown in Krol in U.S. Pat. No. 4,010,385 entitled "Multiplexing Circuitry for Time Sharing a Common Conductor". This circuit includes a plurality of passive networks having multiphase clocking signals associated therewith to selectively enable transmission of information signals over a common conductor. No demultiplexing is shown.
U.S. Pat. No. 3,995,120 of Pachynski, Jr., entitled "Digital Time-Division Multiplexing System" describes a multiplexing scheme wherein N parallel digital signals having an average bit rate of frequency F1 are interleaved by a multiplexer to form a single composite line of bit rate F2. Prior to multiplexing signal gaps having a predetermined duration and having a fixed repetition rate are inserted into each of the N parallel signals. Adding gaps to each digital signal permits the bit rate between gaps to be F2/N.
U.S. Pat. No. 4,593,390 of Hildebrand et al. entitled "Pipeline Multiplexer" illustrates a method of multiplexing a selected one of m initial input signals that comprises N stages of select elements.